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preliminary this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results . 1850 ramtron dr ive, colorado springs, co 80921 (800) 545 - fram, (719) 481 - 7000 rev. 1.1 http:// www.r amtron.com apr. 2011 page 1 of 26 FM31T372/374/ 376/378 system supervisor & temperature compensated r tc (tcxo) with embedded crystal features high integration device replaces multiple parts ? real - time clock (rtc) o embedded 32.768khz crystal o temperature compensated ? 32. 768 k hz clock outpu t ? low - v dd detection drives reset ? watchdog timer ? early power - fail warning/nmi ? two 16 - bit event counters with event driven interrupt output ? serial number with write - lock for security ferroelectric nonvolatile ram ? 4kb, 16kb, 64kb, and 256kb versions ? unlimite d read/write endurance ? 10 year data retention ? nodelay? writes real - time clock/calendar ? temp - compensated using on - chip sensor o ? 5 ppm over - 40 c to +85 c o accuracy ? 2 ? min. per year ? backup current 1 .4 ? a ( max .) at +25c ? seconds through centuries in bcd for mat ? tracks leap years through 2099 ? no external crystal required ? offset register to c orrect for crystal aging ? supports battery or capacitor backup processor companion ? 32 . 768 k hz clock output ? active - low reset output for v dd and watchdog ? programmable v dd res et trip point ? manual reset filtered and debounced ? programmable watchdog timer ? dual battery - backed event counter tracks system intrusions or other events ? event counter driven interrupt output ? comparator for early power - fail interrupt ? 64 - bit programmable se rial number with lock fast two - wire serial interface ? up to 1 mhz maximum bus frequency ? supports legacy timing for 100 khz & 400 khz ? device select pins for up to 4 memory devices ? rtc, supervisor controlled via 2 - wire interface easy to use configurations ? o perates from 2.7 to 5.5v ? small footprint 14 - pin green soic ( - g) ? low operating current ? - 40 ? c to +85 ? c operation description the fm31t37x is a family of integrated devices that includes the most commonly needed functions for processor - based systems. major features include nonvolatile f - ram memory available in various sizes, temperature - compensated real - time clock with embedded crystal , 32. 768 k hz clock output, low - vdd reset, watchdog timer, battery backed event counter, event driven interrupt output, lockab le 64 - bit serial number area, general purpose comparator that can be used for an early power - fail (n mi) interrupt or other purpose, and 2 - wire serial interface to a host microcontroller. the family operates from 2.7 to 5.5v. the real - time clock (rtc) prov ides time and date information in bcd format. it can be permanently powered from external backup voltage source, either a battery or a capacitor. the timekeeper uses an internal 32.768 khz crystal which is factory - calibrated for excellent timekeeping accu racy over the industrial temperature range. the fm31 t37x devi ces integrate 4kb, 16kb, 64kb, and 256kb of f - ram memory. f - ram offers superior write speed and unlimited endurance. this allows the memory to provide system data collection and as read/write ram storage. this memory is truly nonvolatile rather than battery - backed . the processor companion includes commonly needed cpu support functions. supervisory functions include a reset output signal controlled by either a low vdd condition or a watchdog t imeout. /rst goes active when vdd drops below a programmable threshold and remains active for 100 ms after vdd rises above the trip point. a programmable watchdog timer runs from 100 ms to 3 seconds. the watchdog timer is optional, but if enabled it will a ssert the reset signal for 100 ms if not restarted by the host before the timeout. a flag - bit indicates the source of the reset. www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 2 of 26 a general - purpose comparator compares an external input pin to the onboard 1.2v reference. this is useful for generating a po wer - fail interrupt (nmi) but can be used for any purpose. the family also includes a programmable 64 - bit serial number that can be locked making it unalterable. additionally it offers a dual battery - backed event counter that tracks the number of rising or falling edges detected on dedicated input pins. pin configuration pin name function cnt1, cnt2 event counter inputs a0, a1 device select inputs cal/pfo clock calibration and early power - fail output /rst reset in put/output vss ground vbak battery - backup supply pfi early power - fail input /int event counter driven interrupt output fout 32.768 khz clock output sda serial data scl serial clock vdd supply voltage ordering information base configuration memory size operating voltage reset threshold ordering part number fm31t378 256kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm31t3 78 - g fm31t 3 76 64kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm31t3 76 - g fm31t3 74 16kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm31t3 74 - g fm31t3 72 4kb 2 .7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm31t3 72 - g vdd vbak scl sda vss /int f out cal/pfo cnt1 pfi rst a0 a1 cnt2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 3 of 26 figure 1. block diagram pin descriptions pin name type pin description a0, a1 input device select inputs are used to address multiple memories on a serial bus. to select the device the address value on the two pins must match the corresponding bits contained in the device address. the device select pins are pulled down internally. cnt1, cnt2 input event counter inputs: these battery - backed inputs increment counters when an edge is detected on the corresponding cnt pin. the polarity is programmable. these pin s should not be left floating. tie to ground if pins are not used. /int output event counter driven interrupt output. this is a battery backed open - drain output . it goes low for at least 1 00 ms upon changes on either cnt 1 or cnt2 pin. this pin can be left floating if not used. cal/pfo output in normal operation, this is the early power - fail output. in cal mode, it supplies a 512 hz square - wave output for clock calibration. fout output 32.768khz clock output. this is a battery backed open - drain output . this pin can be disabled by setting the foen bit to 0. this pin can be left floating if not used. /rst i/o active low reset output with weak pull - up. also input for manual reset . sda i/o serial data & address: this is a bi - directional line for the two - wire interface. it is open - drain and is intended to be wire - or?d with other devices on the two - wire bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. a pull - up resistor is required. scl input serial clock: the serial clock line for the two - wire interface. data is clocked out of the device on the falling edge, and into the device on the rising edge . the scl input also incorporates a schmitt trigger input for noise immunity. pfi input early power - fail input: typically connected to an unregulated power supply to detect an early power failure. this pin should not be left floating. vbak supply backup supply voltage: a 3v batt ery or a large value capacitor. if no backup supply is used, this pin should be tied to v dd . vdd supply supply voltage f - ram array 2 - wire interface scl sda rst a1, a0 cal/pfo pfi vdd vbak temperature compensated rtc ~2.4v - + rtc registers event counters cnt1 cnt2 special function registers s/n fout /int lockout lockout + - 1.2v watchdog lv detect switched power 512hz battery backed nonvolatile 32. 768 khz temp sensor www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 4 of 25 overview the fm31t37x f amily combines a serial nonvolatile f - ram, a temperature compensated real - time cloc k with embedded crystal , and a p rocessor companion. the companion is a highly integrated peripheral including a processor supervisor, a comparator used for early power - fail warning, non volatile event counters, and a 64 - bit serial number. the fm31 t37x integ rates these complementary but distinct functions that share a common interface in a single package. although monolithic, the product is organized as two logical devices, the f - ram memory , and the rtc /companion. from the system perspective they appear to be two separate devices with uni que ids on the serial bus. the memory is organized as a stand - alone 2 - wire nonvolatile memory with a standard device id value. the real - time clock and supervisor functions are accessed with a separate 2 - wire device id. this allows clock/calendar data to be read while maintaining the most recently used memory address. the clock and supervisor functions are controlled by 2 1 special function registers. the rtc and event counter circuits are maintained by the power source on the vbak pin, allowing them to operate from battery or backup capacitor power when v dd drops below an internally set threshold. each functional block is described below. memory operation the fm31 t37x is a family of products available in different memory sizes including 4kb, 16kb, 64kb, and 256kb. the family is software compatible, all versions use consistent two - byte addressing for the memory device. this makes the lowest density device different from its stand - alone memory counterparts but makes them compatibl e within the entire family. memory is organized in bytes, for example the 4kb memory is 512 x 8 and the 256kb memory is 32,768 x 8. the memory is based on f - ram technology. therefore it can be treated as ram and is read or written at the speed of the two - wire bus with no delays for write operations. it also offers effectively unlimited write endurance unlike other nonvolatile memory technologies. the 2 - wire interface protocol is described further on page 13. the memory array can be write - protected by soft ware. two bits in the processor companion area (wp0, wp1 in register 0bh) control the protection setting as shown in the following table. based on the setting, the protected addresses cannot be written and the 2 - wire interface will not acknowledge any data to protected addresses. the special function registers containing these bits are described in detail below. write protect addresses wp1 wp0 none 0 0 bottom ? 0 1 bottom ? 1 0 full array 1 1 processor companion in addition to nonvolatile ram, the fm31 t37x family incorporates a highly integrated processor companion. it includes a low voltage reset, a programmable watchdog timer, battery - backed event counters with interrupt output, a comparator for early power - fail detection or other purposes, and a 64 - bit s erial number. processor supervisor supervisors provide a host processor two basic functions: detection of power supply fault conditions and a watchdog timer to escape a software lockup condition. all fm31 t37x devices have a reset pin (/rst) to drive the processor reset input during power faults (and power - up) and software lockups. it is an open - drain output with a weak internal pull - up to v dd . this allows other reset sources to be wire - or?d to the /rst pin. when v dd is above the programmed trip point, /rs t output is pulled weakly to v dd . if v dd drops below the reset trip point voltage level (v tp ) the /rst pin will be driven low. it will remain low until v dd falls too low for circuit operation which is the v rst level. when v dd rises again above v tp , /rst wi ll continue to drive low for at least 100 ms (t rpu ) to ensure a robust system reset at a reliable v dd level. after t rpu has been met, the /rst pin will return to the weak high state. while /rst is asserted, serial bus activity is locked out even if a trans action occurred as v dd dropped below v tp . a memory operation started while v dd is above v tp will be completed internally. figure 2 below illustrates the reset operation in response to the v dd voltage. figure 2. low voltage re set vdd vtp t rpu rst www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 5 of 26 the bits vtp1 and vtp0 control the trip point of the low voltage detect circuit. they are located in register 0bh, bits 1 and 0. v tp vtp1 vtp0 2.6v 0 0 2.9v 0 1 3.9v 1 0 4.4v 1 1 the watchdog timer can also be used to assert the reset signal (/rst ). the watchdog is a free running programmable timer. the period can be software programmed from 100 ms to 3 seconds in 100 ms increments via a 5 - bit nonvolatile register. all programmed settings are minimum values and vary with temperature according to th e operating specifications. the watchdog has two additional controls associated with its operation, a watchdog enable bit (wde) and timer restart bits (wr). both the enable bit must be set and the watchdog must timeout in order to drive /rst active. if a r eset event occurs, the timer will automatically restart on the rising edge of the reset pulse. if wde=0, the watchdog timer runs but a watchdog fault will not cause /rst to be asserted low. the wtr flag will be set, indicating a watchdog fault. this settin g is useful during software development and the developer does not want /rst to drive. note that setting the maximum timeout setting (11111b) disables the counter to save power. the second control is a nibble that restarts the timer preventing a reset. the timer should be restarted after changing the timeout value. the watchdog timeout value is located in register 0ah, bits 4 - 0, and the watchdog enable is bit 7. the watchdog is restarted by writing the pattern 1010b to the lower nibble of register 09h. wr iting this pattern will also cause the timer to load new timeout values. writing other patterns to this address will not affect its operation. note the watchdog timer is free - running. prior to enabling it, users should restart the timer as described above. this assures that the full timeout period will be set immediately after enabling. the watchdog is disabled when v dd is below v tp . the following table summarizes the watchdog bits. a block diagram follows. watchdog timeout wdt4 - 0 0ah, bits 4 - 0 watchdog en able wde 0ah, bit 7 watchdog restart wr3 - 0 09h, bits 3 - 0 figure 3. watchdog timer manual reset the /rst pin is bi - directional and allows the fm31 t37x to filter and de - bounce a manual reset switch. the /rst input detects an e xternal low condition and responds by driving the /rst signal low for 100 ms. a manual reset does not set any flags. figure 4. manual reset note that an internal weak pull - up on /rst eliminates the need for additional extern al components. reset flags in case of a reset condition, a flag will be set to indicate the source of the reset. a low v dd reset is indicated by the por flag, register 09h bit 6. a watchdog reset is indicated by the wtr flag, register 09h bit 7. note that the flags are internally set in response to reset sources, but they must be cleared by the user. when the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. early power fail comparator an ear ly power fail warning can be provided to the processor well before v dd drops out of spec. the comparator is used to create a power fail interrupt (nmi). this can be accomplished by connecting the pfi pin to the unregulated power supply via a resistor divid er. an application circuit is shown below. timebase counter watchdog timeout 100 ms clock wde /rst wr3 - 0 = 1010b to restart fm31t37x reset switch rst mcu switch behavior rst fm31t37x drives 100 m s (min.) www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 6 of 26 figure 5. comparator as early power - fail warning the voltage on the pfi input pin is compared to an onboard 1.2v reference. when the pfi input voltage drops below this threshold, th e comparator will drive the cal/pfo pin to a low state. the comparator has 100 mv (max) of hysteresis to reduce noise sensitivity, only for a rising pfi signal. for a falling pfi edge, there is no hysteresis. the comparator is a general purpose device and its application is not limited to the nmi function. the comparator is not integrated into the special function registers except as it shares its output pin with the cal output. when the cal mode is invoked by setting the cal bit (register 00h, bit 2), t he cal/pfo output pin is driven with a 512 hz square wave and the comparator will be ignored. since most users only invoke the cal mode during production, this should have no impact on system operations using the comparator. event counter the fm31 t37x off e rs the user two battery - backed event counters. input pins cnt1 and cnt2 are programmable edge detectors. each clocks a 16 - bit counter. when an edge occurs, the counters will increment their respective registers. counter 1 is located in registers 0dh and 0 eh, counter 2 is located in registers 0fh and 10h. these register values can be read anytime vdd is above vtp, and they will be incremented as long as a valid vbak power source is provided. to read, set the rc bit register 0ch bit 3 to 1. this takes a snap shot of all four counter bytes allowing a stable value even if a count occurs during the read. the registers can be written by software allowing the counters to be cleared or initialized by the system. counts are blocked during a write operation. the two c ounters can be cascaded to create a single 32 - bit counter by setting the cc control bit (register 0ch). when cascaded, the cnt1 input will cause the counter to increment. cnt2 is not used in this mode. figure 6. event counter the control bits for event counting are located in register 0ch. counter 1 polarity is bit c1p, bit 0; counter 2 polarity is c2p, bit 1; the cascade control is cc, bit 2; and the read counter bit is rc bit 3. the polarity bits must be set prior to setti ng the counter value(s). if a polarity bit is changed, the counter may inadvertently increment. if the counter pins are not being used, tie them to ground. event counter driven interrupt o utput the event counter driven interrupt is a battery backed open - d rain output (/int) . a 100ms active low pulse generated for the host microcontroller upon changes on either cnt1 or cnt2 pins. the cnt2 pin will not generate an interrupt if the cc bit is set to ? 1 ? (counter set to cascaded 32 - bit mode). figure 7. event counter driven interrupt o utput serial number a memory location to write a 64 - bit serial number is provided. it is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. the 8 bytes of data a nd the lock bit are all accessed via the device id for the processor companion. therefore the serial number area is separate and distinct from the memory array. the serial number registers can be written an unlimited number of times, so these locations are general purpose memory. however once the lock bit is set the values cannot be altered and the lock cannot be removed. once locked the serial number registers can still be read by the system. fm31t37x int mcu int event occur 100 ms 16 - bit counter cnt1 cc cnt2 c1p c2p 16 - bit counter + - 1.2v ref regulator vdd fm31t37x to mcu nmi input cal/pfo pfi www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 7 of 26 the serial number is located in registers 11h to 18h. the lock b it is snl, register 0bh bit 7. setting the snl bit to ? 1 ? disables writes to the serial number registers, and the snl bit cannot be cleared . real - time clock (tcxo) operation th e real - tim e clock is a timekeeping function that can be battery or c apacitor bac ked for continuous operation. the rtc is operated by a temperature compensated crystal oscillator (tcxo) based on an embedded 32.768 khz crystal. the rtc consists of an oscillator, clock divider, and a register system for user access. it divides down the 32.768 khz time - base and provides a minimum resolution of seconds (1hz). static registers provide the user with read/write access to the time values. it includes registers for seconds, minutes, hours, day - of - the - week, date, months, and years. a block diag ra m ( figure 8) i llustrates the rtc function. the user registers are synchronized with the timekeeper core using r and w bits in register 00h described below. changing the r bit from ? 0 ? to ? 1 ? transfers timekeeping information from the core into holding regi sters that can be read by the user. if a timekeeper update is pending when r is set, then the core will be updated prior to loading the user registers. the registers are frozen and will not be updated again until the r bit is cleared to ? 0 ? . r is used for reading the time. setting the w bit to ? 1 ? locks the user registers. clearing it to ? 0 ? causes the values in the user registers to be loaded into the timekeeper core. w is used for writing new time values. users should be certain not to load invalid values, such as ffh, to the timekeeping registers. updates to the timekeeping core occur continuously except when locked. backup power the real - time clock/calendar is intended to be permanently powered. when the primary system power fails, the voltage on the v d d pin will drop. when v dd is less 2. 4 v the rtc (and event counters) will switch to the backup power supply on v bak . the clock operates at extremely low current in order to maximize battery or capacitor life. however, an advantage of combining a clock funct ion with f - ram memory is that data is not lost regardless of the backup power source. the i bak current varies with temperature and voltage (see dc parametric table). the following graph shows i bak as a function of v bak . th ese curves are useful for calculating backup time when a capacit or is used as the v bak source. figure 8 . i bak vs. v bak voltage the minimum v bak voltage varies linearly with temperature. t he user can expect the minimum v bak voltage to be 1.23v at +85c and 1. 9 0 v at - 40c . th e tested limit is 1.55v at +25 c . the min imum v bak voltage has been characterized at - 40c and +85c but is not 100% tested. figure 9 . v bak ( min.) vs. temperature trickle charger to facilitate capacitor backup , the v bak pin can optionally provide a trickle charge current. when the vbc bit, register 0bh bit 2, is set to ? 1 ? the v bak pin will source approximately 80a until v bak reaches v dd or 3.75v whichever is less. in 3v systems, this charges the capacitor to v dd without an external diode and resistor charger. there is a fast charge mode which is enabled by the fc bit (register 0bh, bit 5). in this mode the trickle charger current is set to approximately 1 ma, allowing a large backup capacitor to charge more quickly. in the case where no battery is used, the v bak pin should be tied to v dd . although v bak may be connected to v ss , t his is not recommended if the companion is used. none of the companion fu nctions will operate below approximately 2. 4 v. www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 8 of 26 note: s ystems using lithium batteries should clear the vbc bit to 0 to prevent battery charging. the v bak circuitry includes an intern al 1 k ? series resistor as a safety element. 32 .768 k hz clock output the 32.768 khz clock (with precision equal to that of the built - in crystal oscillator) can be output via the fout pin. this output is not temperature compensated. this clock can be dis abled by clear ing the foen bit to ?0? . figure 8. real - time clock core block diagram offset/aging compensation the user can expect the rtc to be accurate from the factory. the rtc is calibrated at the factory at room temperature. t he cal bits setting in register 01h will likely be a non - zero value. this is the initial calibration value assigned at the factory prior to shipment. the device may need re - calibrating after solder reflow or after some period of time due to crystal aging . if the user needs to re - calibrate the rtc, the following describes the steps to change the calibration setting . before making changes to the cal bits, t he user can read the se b its to verify the current setting is an expected value . to enter calibration mode, the cal bit in a register 00h must be set to ? 1 ? . when the rtc is in calibration mode, the cal/pfo output pin is dedicated to the calibration function and the power f ail output is temporarily unavailable. calibration operates by applying a digital correction to the counter based on the frequency error. in this mode, the cal/pfo pin is driven with a 512 hz (nominal) square wave. any measured deviation from 512 hz transl ates into a timekeeping error. the 512hz calibration output must be measured at +25 c. this output is not temperature compensated . the user converts the measured error in ppm and writes the appropriate correction value to the calibration register. the corre ction factors are listed in the following table s . positive ppm errors require a negative adjustment that removes pulses. negative ppm errors require a positive correction that adds pulses. positive ppm adjustments have the cals (sign) bit set to ? 1 ? , where as n egative ppm adjustments have cals = 0. the calibration setting is stored in f - ram so is not lost should the backup source fail. it is accessed with bits cal. 5 - 0 in register 01h. this value only can be written when the cal bit is set to ? 1 ? . to exit the c alibration mode, the user must clear the cal bit to a 0. when the cal bit is 0, the cal/pfo pin will revert to the power fail output function. note: temperature compensation is disabled when the cal bit is set to 1. the user should clear this bit to all ow temperature compensation to activate. 32.768 khz crystal oscillator clock divider update logic 512 hz w r seconds 7 bits minutes 7 bits hours 6 bits date 6 bits months 5 bits years 8 bits cf days 3 bits user interface registers 1 hz /oscen 32.768khz www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 9 of 26 calibration adjustments for offset/ aging positive calibration for s low measured c locks measured frequency range at + 25 c error range (ppm) min max min max program calibration register to: 0 512.0000 511.9995 0.00 - 1.02 1000000 1 511.9995 511.9984 - 1.02 - 3.05 1000001 2 511.9984 511.9974 - 3.05 - 5.09 1000010 3 511.9974 511.9964 - 5.09 - 7.12 1000011 4 511.9964 511.9953 - 7.12 - 9.16 1000100 5 511.9953 511.9943 - 9.16 - 11.19 1000101 6 511.9943 511.9932 - 11.19 - 13.22 1000110 7 511.9932 511.9922 - 13.22 - 15.26 1000111 8 511.9922 511.9911 - 15.26 - 17.29 1001000 9 511.9911 511.9901 - 17.29 - 19.33 1001001 10 511.9901 511.9891 - 19.33 - 21.36 1001010 11 511.9891 511.9880 - 21.36 - 23.40 1001011 12 511.9880 511.9 870 - 23.40 - 25.43 1001100 13 511.9870 511.9859 - 25.43 - 27.47 1001101 14 511.9859 511.9849 - 27.47 - 29.50 1001110 15 511.9849 511.9839 - 29.50 - 31.53 1001111 16 511.9839 511.9828 - 31.53 - 33.57 1010000 17 511.9828 511.9818 - 33.57 - 35.60 1010001 18 511.98 18 511.9807 - 35.60 - 37.64 1010010 19 511.9807 511.9797 - 37.64 - 39.67 1010011 20 511.9797 511.9786 - 39.67 - 41.71 1010100 21 511.9786 511.9776 - 41.71 - 43.74 1010101 22 511.9776 511.9766 - 43.74 - 45.78 1010110 23 511.9766 511.9755 - 45.78 - 47.81 1010111 2 4 511.9755 511.9745 - 47.81 - 49.85 1011000 25 511.9745 511.9734 - 49.85 - 51.88 1011001 26 511.9734 511.9724 - 51.88 - 53.91 1011010 27 511.9724 511.9714 - 53.91 - 55.95 1011011 28 511.9714 511.9703 - 55.95 - 57.98 1011100 29 511.9703 511.9693 - 57.98 - 60.02 10 11101 30 511.9693 511.9682 - 60.02 - 62.05 1011110 31 511.9682 511.9672 - 62.05 - 64.09 1011111 32 511.9672 511.9661 - 64.09 - 66.12 1100000 33 511.9661 511.9651 - 66.12 - 68.16 1100001 34 511.9651 511.9641 - 68.16 - 70.19 1100010 35 511.9641 511.9630 - 70.19 - 72.22 1100011 36 511.9630 511.9620 - 72.22 - 74.26 1100100 37 511.9620 511.9609 - 74.26 - 76.29 1100101 38 511.9609 511.9599 - 76.29 - 78.33 1100110 39 511.9599 511.9589 - 78.33 - 80.36 1100111 40 511.9589 511.9578 - 80.36 - 82.40 1101000 41 511.9578 511.9568 - 82.40 - 84.43 1101001 42 511.9568 511.9557 - 84.43 - 86.47 1101010 43 511.9557 511.9547 - 86.47 - 88.50 1101011 44 511.9547 511.9536 - 88.50 - 90.54 1101100 45 511.9536 511.9526 - 90.54 - 92.57 1101101 46 511.9526 511.9516 - 92.57 - 94.60 1101110 47 511.9516 5 11.9505 - 94.60 - 96.64 1101111 48 511.9505 511.9495 - 96.64 - 98.67 1110000 49 511.9495 511.9484 - 98.67 - 100.71 1110001 50 511.9484 511.9474 - 100.71 - 102.74 1110010 51 511.9474 511.9464 - 102.74 - 104.78 1110011 52 511.9464 511.9453 - 104.78 - 106.81 1110100 53 511.9453 511.9443 - 106.81 - 108.85 1110101 54 511.9443 511.9432 - 108.85 - 110.88 1110110 55 511.9432 511.9422 - 110.88 - 112.92 1110111 56 511.9422 511.9411 - 112.92 - 114.95 1111000 57 511.9411 511.9401 - 114.95 - 116.98 1111001 58 511.9401 511.9391 - 11 6.98 - 119.02 1111010 59 511.9391 511.9380 - 119.02 - 121.05 1111011 60 511.9380 511.9370 - 121.05 - 123.09 1111100 61 511.9370 511.9359 - 123.09 - 125.12 1111101 62 511.9359 511.9349 - 125.12 - 127.16 1111110 63 511.9349 511.9339 - 127.16 - 129.19 1111111 www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 10 of 26 n egative calibration for fast measured c locks measured frequency range at + 25 c error range (ppm) min max min max program calibration register to: 0 512.0000 512.0005 0.00 1.02 0000000 1 512.0005 512.0016 1.02 3.05 0000001 2 512.0016 512.0026 3.05 5.09 0000010 3 512.0026 512.0036 5.09 7.12 0000011 4 512.0036 512.0047 7.12 9.16 0000100 5 512.0047 512.0057 9.16 11.19 0000101 6 512.0057 512.0068 11.19 13.22 0000110 7 512.0068 512.0078 13.22 15.26 0000111 8 512.0078 512.0089 15.26 17.29 0001 000 9 512.0089 512.0099 17.29 19.33 0001001 10 512.0099 512.0109 19.33 21.36 0001010 11 512.0109 512.0120 21.36 23.40 0001011 12 512.0120 512.0130 23.40 25.43 0001100 13 512.0130 512.0141 25.43 27.47 0001101 14 512.0141 512.0151 27.47 29.50 0001110 15 512.0151 512.0161 29.50 31.53 0001111 16 512.0161 512.0172 31.53 33.57 0010000 17 512.0172 512.0182 33.57 35.60 0010001 18 512.0182 512.0193 35.60 37.64 0010010 19 512.0193 512.0203 37.64 39.67 0010011 20 512.0203 512.0214 39.67 41.71 0010100 21 5 12.0214 512.0224 41.71 43.74 0010101 22 512.0224 512.0234 43.74 45.78 0010110 23 512.0234 512.0245 45.78 47.81 0010111 24 512.0245 512.0255 47.81 49.85 0011000 25 512.0255 512.0266 49.85 51.88 0011001 26 512.0266 512.0276 51.88 53.91 0011010 27 512.0 276 512.0286 53.91 55.95 0011011 28 512.0286 512.0297 55.95 57.98 0011100 29 512.0297 512.0307 57.98 60.02 0011101 30 512.0307 512.0318 60.02 62.05 0011110 31 512.0318 512.0328 62.05 64.09 0011111 32 512.0328 512.0339 64.09 66.12 0100000 33 512.0339 512.0349 66.12 68.16 0100001 34 512.0349 512.0359 68.16 70.19 0100010 35 512.0359 512.0370 70.19 72.22 0100011 36 512.0370 512.0380 72.22 74.26 0100100 37 512.0380 512.0391 74.26 76.29 0100101 38 512.0391 512.0401 76.29 78.33 0100110 39 512.0401 512. 0411 78.33 80.36 0100111 40 512.0411 512.0422 80.36 82.40 0101000 41 512.0422 512.0432 82.40 84.43 0101001 42 512.0432 512.0443 84.43 86.47 0101010 43 512.0443 512.0453 86.47 88.50 0101011 44 512.0453 512.0464 88.50 90.54 0101100 45 512.0464 512.0474 90.54 92.57 0101101 46 512.0474 512.0484 92.57 94.60 0101110 47 512.0484 512.0495 94.60 96.64 0101111 48 512.0495 512.0505 96.64 98.67 0110000 49 512.0505 512.0516 98.67 100.71 0110001 50 512.0516 512.0526 100.71 102.74 0110010 51 512.0526 512.0536 102.74 104.78 0110011 52 512.0536 512.0547 104.78 106.81 0110100 53 512.0547 512.0557 106.81 108.85 0110101 54 512.0557 512.0568 108.85 110.88 0110110 55 512.0568 512.0578 110.88 112.92 0110111 56 512.0578 512.0589 112.92 114.95 0111000 57 512.0589 5 12.0599 114.95 116.98 0111001 58 512.0599 512.0609 116.98 119.02 0111010 59 512.0609 512.0620 119.02 121.05 0111011 60 512.0620 512.0630 121.05 123.09 0111100 61 512.0630 512.0641 123.09 125.12 0111101 62 512.0641 512.0651 125.12 127.16 0111110 63 51 2.0651 512.0661 127.16 129.19 0111111 www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 11 of 26 register map the tcxo and processor companion functions are accessed via 25 special function registers mapped to a separate 2 - wire device id. the interface protocol is described below. the registers contain timekeepi ng data, control bits, or information flags. a description of each register follows the summary table below. register map summary table nonvolatile = battery - backed = note: when the device is first powered up and program med, all registers must be written because the battery - backed register values cannot be guaranteed. the table below shows the default values of the non - volatile registers. all other register values should be treated as unknown. default register values a ddress hex value 18h 0x00 17h 0x00 16h 0x00 15h 0x00 14h 0x00 13h 0x00 12h 0x00 11h 0x00 0bh 0x 4 0 0ah 0x1f 01h factory programmed data address d7 d6 d5 d4 d3 d2 d1 d0 function range serial number byte 7 serial number 7 ffh serial number byte 6 serial number 6 ffh serial number byte 5 serial number 5 ffh serial number byte 4 serial number 4 ffh serial number byte 3 serial number 3 ffh serial number byte 2 serial number 2 ffh serial number byte 1 serial number 1 ffh serial number byte 0 serial number 0 ffh 10h counter 2 msb event counter 2 msb ffh 0fh counter 2 lsb event counter 2 lsb ffh 0eh counter 1 msb event counter 1 msb ffh 0dh counter 1 lsb event counter 1 lsb ffh 0ch rc cc c2p c1p event count control 0bh snl foen fc wp1 wp0 vbc vtp1 vtp0 companion control 0ah wde - - wdt4 w dt3 wdt2 wdt1 wdt0 watchdog control 09h w tr por lb - wr3 wr2 wr1 wr0 watchdog restart/flags 08h 10 years years years 00-99 07h 0 0 0 10 mo months month 1-12 06h 0 0 10 date date date 1-31 05h 0 0 0 0 0 day day 1-7 04h 0 0 10 hours hours hours 0-23 03h 0 10 minutes minutes minutes 0-59 02h 0 10 seconds seconds seconds 0-59 01h /oscen cals c al5 cal4 cal3 cal2 cal1 cal0 osc/cal control 00h reserved cf reserved reserved reserved cal w r rtc control 18h 17h 11h 16h 15h 14h 13h 12h www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 12 of 26 register description address description 18h serial number byte 7 d7 d6 d5 d4 d3 d2 d1 d0 sn.63 sn.62 sn .61 sn.60 sn.59 sn.58 sn.57 sn.56 upper byte of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 17h serial number byte 6 d7 d6 d5 d4 d3 d2 d1 d0 sn.55 sn.54 sn.53 sn.52 sn.51 sn.50 sn.49 sn.48 byte 6 of the serial numb er. read/write when snl=0, read - only when snl=1. nonvolatile. 16h serial number byte 5 d7 d6 d5 d4 d3 d2 d1 d0 sn.47 sn.46 sn.45 sn.44 sn.43 sn.42 sn.41 sn.40 byte 5 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 15 h serial number byte 4 d7 d6 d5 d4 d3 d2 d1 d0 sn.39 sn.38 sn.37 sn.36 sn.35 sn.34 sn.33 sn.32 byte 4 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 14h serial number byte 3 d7 d6 d5 d4 d3 d2 d1 d0 sn.31 sn.30 sn .29 sn.28 sn.27 sn.26 sn.25 sn.24 byte 3 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 13h serial number byte 2 d7 d6 d5 d4 d3 d2 d1 d0 sn.23 sn.22 sn.21 sn.20 sn.19 sn.18 sn.17 sn.16 byte 2 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 12h serial number byte 1 d7 d6 d5 d4 d3 d2 d1 d0 sn.15 sn.14 sn.13 sn.12 sn.11 sn.10 sn.9 sn.8 byte 1 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 11h seri al number byte 0 d7 d6 d5 d4 d3 d2 d1 d0 sn.7 sn.6 sn.5 sn.4 sn.3 sn.2 sn.1 sn.0 lsb of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 10h counter 2 msb d7 d6 d5 d4 d3 d2 d1 d0 c2.15 c2.14 c2.13 c2.12 c2.11 c2.10 c2 .9 c2.8 event counter 2 msb. increments on overflows from counter 2 lsb. battery - backed, read/write. 0fh counter 2 lsb d7 d6 d5 d4 d3 d2 d1 d0 c2.7 c2.6 c2.5 c2.4 c2.3 c2.2 c2.1 c2.0 event counter 2 lsb. increments on programmed edge event on cnt2 input or overflows from counter 1 msb when cc=1. battery - backed, read/write . 0eh counter 1 msb d7 d6 d5 d4 d3 d2 d1 d0 c1.15 c1.14 c1.13 c1.12 c1.11 c1.10 c1.9 c1.8 event counter 1 msb. increments on overflows from counter 1 lsb. battery - backed, r ead/write. 0dh counter 1 lsb d7 d6 d5 d4 d3 d2 d1 d0 c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 event counter 1 lsb. increments on programmed edge event on cnt1 input. battery - backed, read/write. www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 13 of 26 0ch event counter control d7 d6 d5 d4 d3 d2 d1 d0 - - - - rc cc c2p c1p rc read counter. setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. the rc bit will be automatically cleared. cc counter cascade. when cc=0, the eve nt counters operate independently according to the edge programmed by c1p and c2p respectively. when cc=1, the counters are cascaded to create one 32 - bit counter. the registers of counter 2 represent the most significant 16 - bits of the counter and cnt1 is the controlling input. bit c2p is don?t care when cc=1. battery - backed, read/write. c2p cnt2 detects falling edges when c2p = 0, rising edges when c2p = 1. c2p is don?t care when cc=1. the value of event counter 2 may inadvertently increment if c2p is changed. battery - backed, read/write. c1p cnt1 detects falling edges when c1p = 0, rising edges when c1p = 1. the value of event counter 1 may inadvertently increment if c1p is changed. battery - backed, read/write. 0bh companion control d7 d6 d5 d4 d3 d 2 d1 d0 snl foen fc wp1 wp0 vbc vtp1 vtp0 snl serial number lock. setting to a 1 makes registers 11h to 18h and snl permanently read - only. snl cannot be cleared once set to 1. nonvolatile, read/write. foen 32.768khz frequency output enable. default i s 1 = on. output fout turned off when foen = 0. temperature compensation is not applied to the 32.768khz frequency on the fout pin. fc fast charge: setting fc to ?1? (and vbc=1) causes a ~1 ma trickle charge current to be supplied on v bak . clearing vb c to ?0? disables the charge current. nonvolatile, read/write. wp1 - 0 write protect. these bits control the write protection of the memory array. nonvolatile, read/write. write protect addresses wp1 wp0 none 0 0 bottom ? 0 1 bottom ? 1 0 full array 1 1 v bc vbak charger control. setting vbc to 1 causes ~80 a (fc=0) trickle charge current to be supplied on vbak. clearing vbc to 0 disables the charge current. nonvolatile, read/write. vtp1 - 0 vtp select. these bits control the reset trip point for the low vd d reset function. nonvolatile, read/write. vtp vtp1 vtp0 2.6v 0 0 2.9v 0 1 3.9v 1 0 4.4v 1 1 0ah watchdog control d7 d6 d5 d4 d3 d2 d1 d0 wde - - wdt4 wdt3 wdt2 wdt1 wdt0 wde watchdog enable. when wde=1, a watchdog timer fault will cause the /rst si gnal to go active. when wde = 0 the timer runs but has no effect on /rst, however the wtr flag will be set when a fault occurs. note as the timer is free - running, users should restart the timer using wr3 - 0 prior to setting wde=1. this assures a full watchd og timeout interval occurs. nonvolatile, read/write. wdt4 - 0 watchdog timeout. indicates the minimum watchdog timeout interval with 100 ms resolution. new watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to wr3 - 0. nonvo latile, read/write. watchdog timeout wdt4 wdt3 wdt2 wdt1 wdt0 invalid C default 100 ms 0 0 0 0 0 100 ms 0 0 0 0 1 200 ms 0 0 0 1 0 300 ms 0 0 0 1 1 . . . 2000 ms 1 0 1 0 0 2100 ms 1 0 1 0 1 2200 ms 1 0 1 1 0 . www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 14 of 26 . . 2900 ms 1 1 1 0 1 3000 ms 1 1 1 1 0 disable counter 1 1 1 1 1 09h watchdog restart & flags d7 d6 d5 d4 d3 d2 d1 d0 wtr por lb - wr3 wr2 wr1 wr0 wtr watchdog timer reset flag: when a watchdog timer fault occurs, the wtr bit will be set to 1. it must be cleared by the user. note that both wtr and por could be set if both reset sources have occurred since the flags were cleared by the user. battery - backed. read/write (internally set, user can clear bit). por power - on reset flag: when the /rst pin is activated by a v dd < v tp condition , the por bit will be set to 1. it must be cleared by the user. note that both wtr and por could be set if the reset source has occurred since the flags were cleared by the user. battery - backed. read/write (internally set, user can clear bit). lb low back up flag: on power up, if the vbak source is below the minimum voltage to operate the rtc and event counters, this bit will be set to 1. the user should clear it to 0 when initializing the system. battery - backed. read/write (internally set, user can clear bit). wr3 - 0 watchdog restart: writing a pattern 1010b to wr3 - 0 restarts the watchdog timer. the upper nibble contents do not affect this operation. writing any pattern other than 1010b to wr3 - 0 has no effect on the timer. this allows users to clear the wt r, por, and lb flags without affecting the watchdog timer. battery - backed, write - only. 08h timekeeping C years d7 d6 d5 d4 d3 d2 d1 d0 10 year.3 10 year.2 10 year.1 10 year.0 year.3 year.2 year.1 year.0 contains the lower two bcd digits of the ye ar. lower nibble contains the value for years; upper nibble contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0 - 99. battery - backed, read/write. 07h timekeeping C months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 month month.3 month.2 month.1 month.0 contains the bcd digits for the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1 - 12. b attery - backed, read/write. 06h timekeeping C date of the month d7 d6 d5 d4 d3 d2 d1 d0 0 0 10 date.1 10 date.0 date.3 date.2 date.1 date.0 contains the bcd digits for the date of the month. lower nibble contains the lower digit and operates from 0 t o 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1 - 31. battery - backed, read/write. 05h timekeeping C day of the week d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day.2 day.1 day.0 lower nibble contains a value that correlates to day of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, as the day is not integrated with the date. battery - backed, read/write. 04h timekeeping C hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10 hours.1 10 hours.0 hours.3 hours2 hours.1 hours.0 contains the bcd value of hours in 24 - hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0 - 23. battery - backed, read/write. 03h timekeeping C minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10 min.2 10 min.1 10 min.0 min.3 min.2 min.1 min.0 contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0 - 59. battery - backed, read/write. www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 15 of 26 02h timekeeping C seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10 sec.2 10 sec.1 10 s ec.0 seconds.3 seconds.2 seconds.1 seconds.0 contains the bcd value of seconds. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the range for the register is 0 - 59. battery - ba cked, read/write. 01h osc/control d7 d6 d5 d4 d3 d2 d1 d0 oscen cals cal5 cal4 cal3 cal2 cal1 cal0 /oscen /oscillator enable. when set to 1, the oscillator is halted. when set to 0, the oscillator runs. disabling the oscillator can save battery pow er during storage. on a power - up without battery, this bit is set to 1. battery - backed, read/write. cals calibration sign. determines if the calibration adjustment is applied as an addition to or as a subtraction from the time - base. calibration is explain ed on page 8 . this bit is factory programmed. nonvolatile, read/write. cal.5 - 0 these six bits control the calibration of the clock. these bits are factory programmed. nonvolatile, read/write. 00h flags/control d7 d6 d5 d4 d3 d2 d1 d0 reserved c f reserved reserved reserved cal w r reserved reserved bits. do not use. should remain set to 0. cf century overflow flag. this bit is set to a 1 when the values in the years register overflows from 99 to 00. this indicates a new century, such as going f rom 1999 to 2000 or 2099 to 2100. the user should record the new century information as needed. this bit is cleared to 0 when the flag register is read. it is read - only for the user. battery - backed. cal when set to 1, the cal/pfo pin gives a 512 hz square - wave output for clock audit . when cal bit s et to 0, the clock operates normally, and the cal/pfo pin is controlled by the power fail comparator. the cal bit must be cleared to enable temperature compensation. temperature compensation is not applied to the 512hz frequency on the cal/pfo pin. battery - backed, read/write. w write time. setting the w bit to 1 freezes the clock. the user can then write the timekeeping registers with updated values. resetting the w bit to 0 causes the contents of the time regis ters to be transferred to the timekeeping counters and restarts the clock. battery - backed, read/write. r read time. setting the r bit to 1 copies a static image of the timekeeping core and place it into the user registers. the user can then read them with out concerns over changing values causing system errors. the r bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. battery - backed, read/write. www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 16 of 26 two - wire interface the fm31 t37x em ploys an industr y standard two - wire bus that is familiar to many users. this product is unique since it incorporates two logical devices in one chip. each logical device can be accessed individually. although monolithic, it appears to the system software to be two separat e products. one is a memory device. it has a slave address (slave id = 1010b) that operates the same as a stand - alone memory device. the second device is a real - time clock and processor companion which have a unique slave address (slave id = 1101b). by c onvention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operat ions. any device on the bus that is being controlled is a sla ve. the fm31t37x is a lways a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions: start, stop, data bit, and acknowledge. the figure below illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications section. figure 9. data transfer protocol start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all read and write transactions begin with a start condition. an operation in progress can be aborted by asserting a start condition at any time. abortin g an operat ion using the start condition will ready the fm31 t37x for a new operation. if the power supply drops below t he specified vtp during operation, any 2 - wire transaction in progress will be aborted and the system must issue a start condition prior to perform ing another operation. stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations must end with a stop condition. if an operation is pending when a stop is asserted, the opera tion will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the two conditions des cribed above, the sda signal should not change while scl is high. acknowledge the acknowledge (ack) takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter must release the sda bus to allow the receiv er to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no - acknowledge (nack) and the operation is aborted. the receiver might nack for two distinct reasons. fir st is that a byte transfer fails. in this case, the nack ends the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not se nd an ack to deliberately terminate an operation. for example, during a read operation, the fm31t37x will continue to place data onto the bus as long as the receiver sends acks (and clocks). when a read operation is complete and no more data is needed, the receiver must nack the last byte. if the receiver acks the last byte, this will cause the fm31 t37x to stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 17 of 26 attempt to drive the bus on the next clock while the master is sending a new command such as a stop. slave address the first byte that the fm31 t37x expe cts after a start condition is the slave address. as shown in figures below, the slave address contains the slave id, device select address, and a bit that specifies if the transaction is a read or a write. the fm31 t37x has two slave addresses (slave ids ) associated with two logical devices. to access the memory device, bits 7 - 4 should be set to 1010b. the other logical device within the fm31 t37x is the real - time clock and companion. to acc ess this device, bits 7 - 4 of the slave address should be set to 11 01b. a bus transaction with this slave address will not affect the memory in any way. the figures below illustrate the two slave addresses. the device select bits allow multiple devices of the same type to reside on the 2 - wire bus. the device select bit s (bits 2 - 1) select one of four parts on a two - wire bus. they must match the corresponding value on the external address pins in order to select the device. bit 0 is the read/write bit. a 1 indicates a read operation, and a 0 indicates a write operatio n. figure 10. slave address - memory figure 11. slave address C companion addressing overview C memory after the fm31 t37x acknowledges the slave address, the master can place the memory address on the bu s for a write operation. the address requires two bytes. this is true for all members of the family. therefore the 4kb and 16kb configurations will be addressed differently from stand alone serial memories but the entire family will be upwardly compatible with no software changes. the first is the msb (upper byte). for a given density unused address bits are don?t cares, but should be set to 0 to maintain upward compatibility. following the msb is the lsb (lower byte) which contains the remaining eight add ress bits. the address is latched internally. each access causes the latched address to be incremented automatically. the current address is the value that is held in the latch, either a newly written value or the address following the last access. the cur rent address will be held as long as vdd > vtp or until a new value is written. accesses to the clock do not affect the current memory address. reads always use the current address. a random read address can be loaded by beginning a write operation as expl ained below. after transmission of each data byte, just prior to the acknowledge, the fm31 t37x increments the internal address. this allows the next sequential byte to be accessed with no additional addressing externally. after the last address is reache d, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. addressing overview C rtc & companion the rtc and processor companion operate in a similar manner to the me mory, except that it uses only one byte of address. addresses 00h to 18h correspond to special function registers. attempting to load addresses above 18h is an illegal condition; the fm31 xxt37x will return a nack and abort the 2 - wire transaction. data tr ansfer after the address information has been transmitted, data transfer between the bus master and the f m31 t37x begins. for a read, the fm 31 t37x will place 8 data bits on the bus then wait for an ack from the master. if the ack occurs, the fm31 t37x will t ransfer the next byte. if the ack is not sent, the fm31 t37x will end the read operation. for a write operation, the fm31 t37x will accept 8 data b its from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memo ry write operation all memory writes begin with a slave address, then a memory address. the bus master indicates a write operation by setting the slave address lsb to a 0. after addressing, the bus master sends each byte of data to the memory and the memor y generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range 1 0 1 x a1 a0 r/w slave id 7 6 5 4 3 2 1 0 device select 1 1 0 1 0 x a1 a0 r/w slave id device select 7 6 5 4 3 2 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 18 of 26 is reached internally, the address counter will wrap to 0000h. internally, the actual memory write occurs after the 8 th data bit is transfe rred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using a start or stop condition prior to the 8 th data bit. the figures below illustrate a si ngle - and multiple - writes to memory. figure 12. single byte memory write figure 13. multiple byte memory write memory read operation there are two types of memory read operations. they are current address read and selective address read. in a current address read, the fm31 t37x uses the internal address latch to supply the address. in a selective read, the user performs a procedure to first set the address to a specific value. current address & sequential read as mentioned above the fm31 t3 7x u ses an internal latch to supply the address for a read operation. a current address read uses the existing value in the address latch as a starting place for the read operation. the system reads from the address immediately following that of the last o peration. to perform a current address read, the bus master supplies a slave address with the lsb set to 1. this indicates that a read operation is requested. after receiving the complete device address, the fm31 t37x will begin shifting data out from the current address o n the next clock. the current address is the value held in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multip le byte transfers. after each byte the internal address counter will be incremented. each time the bus master acknowledges a byte, this indicates that the fm31 t37x should read out the next sequential byte. there are four ways to terminate a read operat ion. failing to properly terminate the read will most likely create a bus contention as the fm31 t37x at tempts to read out additional data onto the bus. the four valid methods follow. 1. the bus master issues a nack in the 9 th clock cycle and a stop in the 1 0 th clock cycle. this is illustrated in the diagrams below and is preferred. 2. the bus master issues a nack in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. 4. the bus master issues a start in the 9 th clock cycle. if the internal address reaches the top of memory, it will wrap around to 0000h on the next read cycle. the figures below show the proper operation for current address reads. by fm31t37x by fm31t37x s a slave address 0 address msb a data byte a p by master by fm31xxx start address & data stop acknowledge address lsb a s a slave address 0 address msb a data byte a p by master by fm31xxx start address & data stop acknowledge address lsb a data byte a www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 19 of 26 selective (random) read there is a simple technique that allows a user t o select a random address location as the starting point for a read operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm31 t37x acknowledges the address, the bus master issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a 1. the operation is now a read from the current address. read operations are illustrated be low. rtc /companion write operation all rtc and companion writes operate in a similar manner to memory writes. the distinction is that a different device id is used and only one byte address is needed instead of two. figure 16 illustrates a single byte wr ite to this device. rtc /companion read operation as with writes, a read operation begins with the slave address. to perform a register read, the bus master supplies a slave address with the lsb set to 1. this indicates that a read operation is requested. after receiving the complete slave address, the fm31t37x will begin shifting data out from the current register address on the next clock. auto - increment operates for the special function registers as with the memory address. a current address read for the registers look exactly like the memory except that the device id is different. the fm31 t37x co ntains two separate address registers, one for the memory address and the other for the register address. this allows the contents of one address register to b e modified without affecting the current address of the other register. for example, this would allow an interrupted read to the memory while still providing fast access to an rtc register. a subsequent memory read will then continue from the memory addres s where it previously left off, without requiring the load of a new memory address. however, a write sequence always requires an address to be supplied. figure 14. current address memory read figure 15. sequential memory read by fm31t37x by fm31t37x s a slave address 1 data byte 1 p by master by fm31xxx start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by fm31xxx start address stop acknowledge no acknowledge data data byte a acknowledge www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 20 of 26 figure 16 . selective (random) memory read figure 17. byte register write note: it is requir ed that regist er address bits a7 - a5 are cleared (zeroes) . addressing f - ram array in the fm31 t37x family the fm31 t37x famil y includes 256kb, 64kb, 16kb, and 4kb memory densities. the following 2 - byte address field is shown for each density. table 4. two - byte memory address part # 1 st address byte 2 nd address byte fm31t378 x a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 fm31t3 76 x x x a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 fm31t374 x x x x x a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 FM31T372 x x x x x x x a8 a7 a6 a5 a4 a3 a2 a1 a0 s a slave address 0 address a data byte a p by master start address & data stop acknowledge 0 0 0 by fm31t37x by fm31t37x s a slave address 1 data byte 1 p by master by fm31xxx start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 21 of 26 electrical specifications absolute maximum ratings symbol description ratings v dd power su pply voltage with respect to v ss - 1.0v to +7.0v v in voltage on any signal pin with respect to v ss - 1.0v to +7.0v and v in v dd +1.0v * v bak backup supply voltage - 1.0v to +4.5v t stg storage temperature - 55 ? c to + 125 ? c t lead lead temperature (solderin g, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 2kv 1 .25 kv 100v package moisture sensitivity level msl - 1 * th e v in < v dd +1.0v restriction does not apply to the scl and sda inputs which do not employ a diode to v dd . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functiona l operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating conditions ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v unless otherwise specified) symbol parameter min typ max units notes v dd main power supply 2.7 5.5 v 7 i dd v dd supply current @ scl = 100 khz @ scl = 400 khz @ scl = 1 mhz 500 900 1500 ? a ? a ? a 1 i sb standby current for v dd < 5.5v for v dd < 3.6v 150 120 ? a ? a 2 v bak rtc backup supply voltage @ t a = +25 o c to +85 o c @ t a = - 40o c to +2 5 o c 1.55 1. 9 3.75 3.75 v v v 9 i bak rtc backup supply current @ t a = +25oc , v bak = 3.0v @ t a = +85oc , v bak = 3.0v @ t a = +25oc , v bak = 2 .0v @ t a = +85oc , v bak = 2 .0 v 1 .4 2. 1 1.15 1.75 ? a ? a ? a ? a 4 i baktc trickle charge current with v bak =0v fast charge off (fc = 0) fast charge on (fc = 1) 5 0 200 1 20 2500 ? a ? a 10 v tp0 v dd trip point voltage, vtp(1:0) = 00b 2.55 2.6 2.70 v 5 v tp1 v dd trip point voltage, vtp(1:0) = 01b 2.80 2.9 3.00 v 5 v tp2 v dd trip point voltage, vtp(1:0) = 10b 3.80 3.9 4.00 v 5 v tp3 v dd trip point voltage, vtp(1:0) = 11b 4.25 4.4 4.50 v 5 v rst v dd for valid /rst @ i ol = 8 0 ? a at v ol v bak > v bak min v bak < v bak min 0 1.6 v v 6 i li input leakage current ? 1 ? a 3 i lo output leakage current ? 1 ? a 3 v il input low voltage all inputs except those listed below cnt1 - 2 battery backed (v dd < 2.4 v) cnt1 - 2 (v dd > 2.4 v) - 0.3 - 0.3 - 0.3 0.3 v dd 0.5 0.8 v v v 8 continued ? www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 22 of 26 dc ope rating conditions, continued ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v unles s otherwise specified) symbol parameter min typ max units ? notes v ih input high voltage all inputs except those listed below pfi (comparator input) cnt1 - 2 battery backe d (v dd < 2.4 v) cnt1 - 2 v dd > 2.4 v 0.7 v dd - v bak C 0.5 0.7 v dd v dd + 0.3 3.75 v bak + 0.3 v dd + 0.3 v v v v v ol output low voltage (i ol = 3 ma), fout, /int, /rst - 0.4 v v oh output high voltage (i oh = - 2 ma) 2.4 - v r rst pull - up resistance fo r /rst inactive 50 400 k ? r in input resistance (pulldown) a1 - a0 for v in = v il max a1 - a0 for v in = v ih min 20 1 k ? m ? v pfi power fail input reference voltage 1.175 1.20 1.225 v v hys power fail input (pfi) hysteresis (rising) - 100 mv not es 1. scl toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. all inputs at v ss or v dd, static . stop command issued. 3. v in or v out = v ss to v dd . does not apply to a0, a1, pfi, or /rst pins. 4. v bak = 3.0v, v dd < 2.4v, oscillator running, cnt1 - 2 at vss or v bak . 5. /rst is asserted low when v dd < v tp . 6. the minimum v dd to guarantee the level of /rst remains a valid v ol level. 7. full complete operation. supervisory circuits, rtc, etc operate to lower voltages as specified. 8. includes /rst input detection of exter nal reset condition to trigger driving of /rst signal by fm31 t37x . 9. the v bak trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 10. v bak will source current when trickle charge is enabled (vbc bit=1), v dd > v bak , and v bak < v bak max. ac parameters ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v, c l = 100 pf unless otherwise specified) symbol parameter min max min max min max units notes f scl scl clock frequency 0 100 0 400 0 1000 khz t low clock low period 4.7 1.3 0.6 ? s t high clock high period 4.0 0.6 0.4 ? s t aa scl low to sda data out valid 3 0.9 0.55 ? s t buf bus free before new transmission 4.7 1.3 0.5 ? s t hd:sta start condition hold time 4.0 0.6 0.25 ? s t su:sta start condition s etup for repeated start 4.7 0.6 0.25 ? s t hd:dat data in hold time 0 0 0 ns t su:dat data in setup time 250 100 100 ns t r input rise time 1000 300 300 ns 1 t f input fall time 300 300 100 ns 1 t su:sto stop condition setup time 4.0 0.6 0.25 ? s t dh data output hold (from scl @ vil) 0 0 0 ns t sp noise suppression time constant on scl, sda 50 50 50 ns all scl specifications as well as start and stop conditions apply to both read and write operations. rtc frequency characteri stics symbol parameter min typ max units f out fout clock frequency - 32. 768 - k hz f/f frequency stability vs. t emperature 0 ? c to +45 ? c 3 ppm - 40 ? c to +85 ? c 5 ppm www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 23 of 26 data retention ( t a = - 40 ? c to + 85 ? c, v dd = 2.7 v to 5.5v) symbol parameter min units notes t dr data retention 10 years supervisor timing ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v) symbol parameter min max units notes t rpu /rst active (low) after v dd >v tp 100 200 ms t intp pulse width of /int active 100 200 ms t rnr v dd < v tp noise immunity 10 25 ? s 1 t vr v dd rise time 50 - ? s/v 1,2 t vf v dd fall time 100 - ? s/v 1,2 t wdp pulse width of /rst for watchdog reset 100 200 ms t wdog timeout of watchdog t dog 2*t dog ms 3 f cnt frequency of event counters 0 10 mhz notes 1 this parameter is characterized but not tested. 2 slope measured at any point on v dd wav eform. 3 t dog is the programmed time in register 0ah, v dd > v tp and t rpu satisfied. /rst timing /int pulse width cnt1, cnt 2 t intp int vdd vtp vrst rst t rpu t rnr www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 24 of 26 ac test conditions equivalent ac load circuit input pulse levels 0.1 v dd to 0 .9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters ap ply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant data sheet sections. these diagrams illustrate the timing parameters only. read bus timing write bus timing t su : sta start t r ` t f stop start t buf t high 1 / f scl t low t sp t sp acknowledge t hd : dat t su : d at t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda 5.5v output 1700 ? 100 pf www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 25 of 26 mechanical drawing 14 - pin soic (jedec standard) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: x xx xxx= pa rt number, p= package type ( - g) lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm31 t378 , green soic package, year 2010, work week 20 fm31 t378 - g a0 0003g ric 1020 xxxx xxx - p ll llll l ric yyww p i n 1 3 . 9 0 0 . 1 3 6 . 0 0 0 . 2 0 8 . 6 4 0 . 1 0 0 . 1 0 0 . 2 5 1 . 3 5 1 . 7 5 0 . 3 3 0 . 5 1 1 . 2 7 0 . 1 0 m m 0 . 2 5 0 . 5 0 4 5 0 . 4 0 1 . 2 7 0 . 1 9 0 . 2 5 0 - 8 r e c o m m e n d e d p c b f o o t p r i n t 7 . 7 0 0 . 6 5 1 . 2 7 2 . 0 0 3 . 7 0 www.datasheet.co.kr datasheet pdf - http://www..net/
FM31T372/374/376/378 - g rev. 1.1 apr. 2011 page 26 of 26 revision history revision date summary 1.0 6/14/2010 preliminary status. 1.1 4/ 18 /2011 document ation updates and clarifications. changed i bak limits. www.datasheet.co.kr datasheet pdf - http://www..net/

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